Multiprocessor arrangements typically require to have some means of communication between the individual processors. One known method to provide such communication is by means of shared memory. In order to transfer information from a first processor to a second processor, the first processor can write data to the shared memory, and the data be read by the second processor.
So-called “time-sliced” memory is a convenient method to provide such a shared memory. As will be familiar to those skilled in the art, and described in more detail hereinbelow, memory can in some cases operate with a faster clock cycle than can processors. Taking as an example a situation in which a memory clock can run three times the speed of each of three processors. Then, multiple accesses to the memory can be made during a single (processor) clock cycle. If the processor clock cycles—three in this instance—are staggered in time, access to the memory may be distributed in time between the three processors. Such a modified von Neuman architecture, which is commonly referred to as time-slicing, is known and used for instance in the DSP32C device supplied by Lucent Technologies.
Communication between processors in multiprocessor arrangements by time-slicing suffers from a disadvantage, in that the number of processors which can share information is limited—in the example above, for instance, at most 3 processors can be involved in the time slicing.